IFADCENNEGRES=disable, IFADCVCMLVL=vcm_475mV, IFADCENSUBGMODE=fullspeed_mode, IFADCNEGRESVCM=r210k_x_1uA, IFADCTZ=default_zero, IFADCENXOBYPASS=disable_bypass, IFADCNEGRESCURRENT=i1p0u
| IFADCVCMLVL | IFADCVCMLVL 0 (vcm_475mV): undefined 1 (vcm_500mV): undefined 2 (vcm_525mV): undefined 3 (vcm_550mV): undefined 4 (vcm_575mV): undefined 5 (vcm_600mV): undefined 6 (vcm_625mV): undefined 7 (cm_650mV): undefined |
| IFADCENNEGRES | IFADCENNEGRES 0 (disable): undefined 1 (enable): undefined |
| IFADCNEGRESCURRENT | IFADCNEGRESCURRENT 0 (i1p0u): undefined 1 (i1p5u): undefined 2 (i2p0u): undefined 3 (i2p5u): undefined 4 (i2p0u2): undefined 5 (i2p5u2): undefined 6 (i3p0u): undefined 7 (i3p5u): undefined |
| IFADCNEGRESVCM | IFADCNEGRESVCM 0 (r210k_x_1uA): undefined 1 (r210k_x_1uA2): undefined 2 (r100k_x_2uA): undefined 3 (r50k_x_3uA): undefined |
| IFADCENSUBGMODE | IFADCENSUBGMODELV 0 (fullspeed_mode): undefined 1 (subg_mode): undefined |
| IFADCTZ | IFADCTZ 0 (default_zero): undefined 1 (illegal_mode): undefined 2 (half_zero): undefined 3 (illegal_mode2): undefined 4 (quarter_zero): undefined 5 (illegal_mode3): undefined 6 (illegal_mode4): undefined 7 (illegal_mode5): undefined |
| IFADCENXOBYPASS | IFADCENXOBYPASS 0 (disable_bypass): undefined 1 (enable_bypass): undefined |